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rev.1.00, may . 24.2007, page 1 of 15 r1lv0416d series 4m sram (256-kword 16-bit) rej03c0311-0100 rev.1.00 may.24.2007 description the r 1 lv0416d i s a 4-m b i t st at i c r a m organi zed 256-kword 16-bi t , fabri cat ed by r e nesas's hi gh-performance 0.15 m c m os and tft t echnol ogi es. r 1 lv0416d seri es has rea l i zed hi gher densi t y, hi gher performance and l o w power consumpt i on. the r 1 lv0416d seri es offers l o w power st andby power di ssi pat i on; t h erefore, i t i s sui t abl e for bat t ery backup syst ems. the r 1 lv0416d seri es i s packaged i n a 44-pi n t h i n smal l out l i ne mount devi ce, or a 48-bal l fi ne pi t c h bal l gri d array. features ? si ngl e 3.0 v suppl y: 2.7 v t o 3.6 v ? fast access time: 55/70 ns (max) ? power di ssi pat i on: ? st andby: 3 w (typ) (v cc = 3.0 v) ? equal access and cycle times ? c o mmon dat a i nput and out put . ? three state output ? b a t t e ry backup operat i on. ? 2 chi p sel ect i on for bat t e ry backup ? temperat ure r a nge: -40 t o +85 c
r1lv0416d series ordering information type no. access time package r1lv0416dsb-5si 55 ns 400-mil 44-pin plastic tsop ii r1lv0416dsb-7li 70 ns ptsb0044ga-a (44p3w -h) r1lv0416dbg-5si 55 ns 48-ball csp with 0.75 mm ball pitch r 1 l v 0 4 1 6 d b g - 7 l i 7 0 n s ptbg0048hb-a (48fhh) rev.1.00, may . 24.2007, page 2 of 15
r1lv0416d series pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a4 a3 a2 a1 a0 cs1# i/o0 i/o1 i/o2 i/o3 v v i/o4 i/o5 i/o6 i/o7 we# a17 a16 a15 a14 a13 cc ss a5 a6 a7 oe# ub# lb# i/o15 i/o14 i/o13 i/o12 v v i/o11 i/o10 i/o9 i/o8 cs2 a8 a9 a10 a11 a12 cc ss (top view) 44-pin tsop (top view) 48-ball csp a b c d e f g h 1 2 3 4 5 6 lb# i/o8 i/o9 v ss v cc i/o14 i/o15 nc oe# ub# i/o10 i/o11 i/o12 i/o13 nc a8 a3 a5 a17 nc a14 a0 a12 a9 a1 a4 a6 a7 a16 a15 a13 a10 a2 cs1# i/o1 i/o3 i/o4 i/o5 we# a11 cs2 i/o0 i/o2 v cc v ss i/o6 i/o7 nc pin description pin name function a0 to a17 address input i/o0 to i/o15 data input/output cs1# ( cs1 ) chip select 1 cs2 chip select 2 oe# ( oe ) o u t p u t e n a b l e we# ( we ) w r i t e e n a b l e lb# ( lb ) lower byte select ub# ( ub ) upper byte select v cc p o w e r s u p p l y v ss g r o u n d n c n o c o n n e c t i o n rev.1.00, may . 24.2007, page 3 of 15
r1lv0416d series block diagram ? i/o0 i/o15 cs2 we# oe# a0 a1 a2 a4 a17 v v cc ss row decoder memory matrix 2,048 x 2,048 column i/o column decoder input data control control logic a5 a13 a7 a8 a9 a10 a11 a12 a6 a14 a15 a16 cs1# lb# ub# a3 lsb msb lsb msb rev.1.00, may . 24.2007, page 4 of 15
r1lv0416d series operation table cs1# cs2 we# oe# ub# lb# i/o0 to i/o7 i/o8 to i/o15 operation h h i g h - z h i g h - z s t a n d b y l h i g h - z h i g h - z s t a n d b y h h h i g h - z h i g h - z s t a n d b y l h h l l l d o u t d o u t r e a d l h h l h l d o u t h i g h - z lower byte r e a d l h h l l h h i g h - z d o u t upper byte r e a d l h l l l d i n d i n w r i t e l h l h l din high-z lower byte write l h l l h high-z din upper byte write l h h h h i g h - z h i g h - z o u t p u t d i s a b l e note: h: v ih , l: v il , : v ih or v il absolute maximum ratings p a r a m e t e r s y m b o l v a l u e u n i t power supply voltage relative to v ss v cc ? 0.5 to +4.6 v terminal voltage on any pin relative to v ss v t ? 0.5 * 1 to v cc + 0 . 3 * 2 v power dissipation p t 0 . 7 w operating tem p e r a t u r e 1 t o p r ? 40 to + 85 c storage temperature range tstg ? 65 to + 150 c storage temperature range under bias tbias ? 40 to + 8 5 c notes: 1. v t min: ? 3.0 v for pulse half-width 30 ns. 2. maximum voltage is + 4 .6 v. dc operating conditions p a r a m e t e r s y m b o l m i n t y p m a x u n i t n o t e v cc 2 . 7 3 . 0 3 . 6 v supply voltage v ss 0 0 0 v input high voltage v ih 2 . 2 ? v cc + 0.3 v input low voltage v il ? 0.3 ? 0 . 6 v 1 ambient temperature range ta ? 40 ? + 85 c note: 1. v il min: ? 3.0 v for pulse half-width 30 ns. rev.1.00, may . 24.2007, page 5 of 15
r1lv0416d series dc characteristics p a r a m e t e r s y m b o l m i n t y p max u nit t est conditions input leakage current |i li | ? ? 1 a vin = v ss to v cc output leakage current |i lo | ? ? 1 a cs1# = v ih or cs2 = v il or oe# = v ih or w e # = v il or lb# = ub# = v ih , v i/o = v ss to v cc operating current i cc ? ? 20 ma cs1# = v il , cs2 = v ih , others = v ih /v il , i i/o = 0 ma i cc1 ? ? 25 ma min. cycle, duty = 100%, i i/o = 0 ma, cs1# = v il , cs2 = v ih , others = v ih /v il average operating current i cc2 ? ? 5 ma cycle time = 1 s, duty = 100%, i i/o = 0 ma, cs1# 0.2 v, cs2 v cc ? 0.2 v v ih v cc ? 0.2 v, v il 0.2 v standby current i sb ? 0.1 * 1 0.3 ma cs2 = v il to +85 c i sb1 ? ? 1 0 a to +70 c i sb1 ? ? 8 a to +40 c i sb1 ? ? 3 a ? 5si to +25 c i sb1 ? 1 * 1 2 . 5 a to +85 c i sb1 ? ? 2 0 a to +70 c i sb1 ? ? 1 6 a to +40 c i sb1 ? ? 1 0 a standby current ? 7li to +25 c i sb1 ? 1 * 1 1 0 a vin 0 v (1) 0 v cs2 0.2 v or (2) cs1# v cc ? 0.2 v, cs2 v cc ? 0.2 v or (3) lb# = ub# v cc ? 0.2 v, cs2 v cc ? 0.2 v, cs1# 0.2 v average values v oh 2 . 4 ? ? v i oh = ? 1 ma output high voltage v oh2 v cc ? 0.2 ? ? v i oh = ? 100 a v ol ? ? 0 . 4 v i ol = 2 ma output low voltage v ol 2 ? ? 0 . 2 v i ol = 100 a note: 1. typical values are at v cc = 3 . 0 v, ta = +2 5 c and specified loadi ng, and not guaranteed. capacitance (ta = +25 c , f = 1.0 m h z) p a r a m e t e r s y m b o l m i n t y p m a x u n i t test conditions note input capacitance cin ? ? 8 pf vin = 0 v 1 input/output capacitance c i/o ? ? 1 0 p f v i/o = 0 v 1 note: 1. this parameter is sampled and not 100% tested. rev.1.00, may . 24.2007, page 6 of 15
r1lv0416d series ac characteristics (ta = -40 t o +85c , v cc = 2.7 v t o 3.6 v) test conditions input pul se l e vel s : v il = 0.4 v, v ih = 2.4 v 50 pf dout rl=500 ? 1.4 v output load ? input ri se and fal l t i m e: 5 ns ? input / out put t i m i ng reference l e vel s : 1.4 v ? out put l o ad: see fi gures (incl udi ng scope and j i g) rev.1.00, may . 24.2007, page 7 of 15
r1lv0416d series read cycl e r1lv0416d - 5 s i - 7 l i p a r a m e t e r s y m b o l m i n m a x m i n m a x u n i t n o t e s read cycle time t rc 5 5 ? 7 0 ? n s address access time t aa ? 5 5 ? 7 0 n s t acs1 ? 5 5 ? 7 0 n s chip select access time t acs2 ? 5 5 ? 7 0 n s output enable to output valid t oe ? 3 5 ? 4 0 n s output hold from address change t oh 1 0 ? 1 0 ? n s lb#, ub# access time t ba ? 5 5 ? 7 0 n s t cl z1 1 0 ? 1 0 ? n s 2 , 3 chip select to output in low-z t cl z2 1 0 ? 1 0 ? n s 2 , 3 lb#, ub# disable to low-z t blz 5 ? 5 ? n s 2 , 3 output enable to output in low-z t ol z 5 ? 5 ? n s 2 , 3 t chz1 0 20 0 25 ns 1, 2, 3 chip deselect to output in high-z t chz2 0 20 0 25 ns 1, 2, 3 lb#, ub# disable to high-z t bhz 0 20 0 25 ns 1, 2, 3 output disable to output in high-z t ohz 0 20 0 25 ns 1, 2, 3 rev.1.00, may . 24.2007, page 8 of 15
r1lv0416d series write cycle r1lv0416d - 5 s i - 7 l i p a r a m e t e r s y m b o l m i n m a x m i n m a x u n i t n o t e s write cycle time t wc 5 5 ? 7 0 ? n s address valid to end of write t aw 5 0 ? 6 0 ? n s chip selection to end of write t cw 5 0 ? 6 0 ? n s 5 w r ite pulse width t wp 4 0 ? 5 0 ? n s 4 lb#, ub# valid to end of write t bw 5 0 ? 5 5 ? n s address setup time t as 0 ? 0 ? n s 6 write recovery time t wr 0 ? 0 ? n s 7 data to write time overlap t dw 2 5 ? 3 0 ? n s data hold from write time t dh 0 ? 0 ? n s output active from end of write t ow 5 ? 5 ? n s 2 output disable to output in high-z t ohz 0 2 0 0 2 5 n s 1 , 2 , 3 w r ite to output in high-z t whz 0 2 0 0 2 5 n s 1 , 2 notes: 1. t chz , t ohz , t whz and t bhz are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. this parameter is sampled and not 100% tested. 3. at any given temper ature and voltage condition, t hz max is less than t lz min both for a given device and from device to device. 4. a write occurs during the overlap of a low cs1#, a high cs2, a low w e # and a low lb# or a low ub#. a write begins at the latest transition am ong cs1# going low, cs2 going high, w e # going low and lb# going low or ub# going low. a write ends at the earliest transition among cs1# going hi gh, cs2 going low, w e # going high and lb# going high or ub# going high. t wp is measured from the beginning of write to the end of write. 5. t cw is measured from the later of cs1# going low or cs2 going high to the end of write. 6. t as is measured from the address va lid to the beginning of write. 7. t wr is measured from the earliest of cs1# or we# goi ng high or cs2 going low to the end of write cycle. rev.1.00, may . 24.2007, page 9 of 15
r1lv0416d series timing waveform read t i mi ng waveform (we# = v ih ) t aa t acs1 t acs2 t clz2 t clz1 t blz t ba t oh t rc valid data address dout valid address high impedance cs1# cs2 lb#, ub# oe# * 1, 2, 3 * 1, 2, 3 * 2, 3 * 2, 3 * 2, 3 * 1, 2, 3 t olz * 2, 3 * 1, 2, 3 t oe t chz1 t chz2 t bhz t ohz rev.1.00, may . 24.2007, page 10 of 15
r1lv0416d series write timing waveform (1) (we# c l ock) address we# t wc t aw t wp * 4 t wr * 7 t cw * 5 t cw * 5 t bw t as * 6 t ow * 2 t whz * 1, 2 t dw t dh valid address valid data cs1# lb#, ub# dout din high impedance cs2 rev.1.00, may . 24.2007, page 11 of 15
r1lv0416d series write timing waveform (2) (c s# c l ock, oe# = v ih ) address we# t wc t aw t wp * 4 t wr * 7 t cw * 5 t cw * 5 t bw t as * 6 t dw t dh valid address valid data lb#, ub# dout din high impedance cs2 cs1# rev.1.00, may . 24.2007, page 12 of 15
r1lv0416d series write timing waveform (3) (lb # , ub # c l ock, oe# = v ih ) address we# t wc t aw t wp * 4 t cw * 5 t cw * 5 t bw t wr * 7 t dw t dh valid address valid data lb#, ub# dout din high impedance cs2 cs1# t as * 6 rev.1.00, may . 24.2007, page 13 of 15
r1lv0416d series low v cc data retention characteristics (ta = -40 t o +85c ) p a r a m e t e r s y m b o l m i n ty p m a x u nit t est c o n d i t i o n s v cc for data retention v dr 2 . 0 ? ? v vin 0v (1) 0 v cs2 0.2 v or (2) cs2 v cc ? 0.2 v, cs1# v cc ? 0.2 v or (3) lb# = ub# v cc ? 0.2 v, cs2 v cc ? 0.2 v, cs1# 0.2 v to +85 c i ccdr ? ? 1 0 a to +70 c i ccdr ? ? 8 a to +40 c i ccdr ? ? 3 a ? 5si to +25 c i ccdr ? 1 * 1 2 . 5 a to +85 c i ccdr ? ? 2 0 a to +70 c i ccdr ? ? 1 6 a to +40 c i ccdr ? ? 1 0 a data retention current ? 7li to +25 c i ccdr ? 1 * 1 1 0 a v cc = 3.0 v, vin 0v (1) 0 v cs2 0.2 v or (2) cs2 v cc ? 0.2 v, cs1# v cc ? 0.2 v or (3) lb# = ub# v cc ? 0.2 v, cs2 v cc ? 0.2 v, cs1# 0.2 v average values chip deselect to data retention time t cdr 0 ? ? n s operation recovery time t r 5 ? ? m s see retention waveform note: 1. typical values are at v cc = 3 . 0 v, ta = +2 5 c and specified loadi ng, and not guaranteed. rev.1.00, may . 24.2007, page 14 of 15
r1lv0416d series rev.1.00, may . 24.2007, page 15 of 15 lo w v cc data retention timing waveform (1) (c s1# c ont rol l ed) cc v 2.2 v 2.7 v 0 v cs1# t cdr t r cs1# v ? 0.2 v cc dr v data retention mode cc v 2.7 v 0.6 v 0 v cs2 cdr t r 0 v cs2 0.2 v dr v data retention mode t < < cc v 2.2 v 2.7 v 0 v lb#, ub# t cdr t r lb#, ub# v ? 0.2 v cc dr v data retention mode lo w v cc data retention timing waveform (2) (cs2 controlled) lo w v cc data retention timing waveform (3) (lb#, ub# controlled)
revision history r1lv0416d series data sheet contents of modification rev. date page description 0.01 dec. 25, 2006 ? initial issue 1.00 may. 24, 2007 2 3 4 5 5 6 7 14 ordering information r1lv0416dsb-5s% to r1lv0416dsb-5si r1lv0416dsb-7l% to r1lv0416dsb-7li r1lv0416dbg-5s% to r1lv0416dbg-5si r1lv0416dbg-7l% to r1lv0416dbg-7li pin arrangement a6 to a13, a13 to a6 change of block diagram absolute maximum ratings: dele tion of r ver. specification dc operating conditions: deleti on of r ver. specification dc characteristics i sb1 (-5si) (to +25 c) max: 3 a to 2.5 a ac characteristics: change of test conditions low v cc data retention characteristics i ccdr (-5si) (to +25 c) max: 3 a to 2.5 a deletion of note 2
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